The present invention relates generally to flash memory cell devices and more specifically, to improvements in systems and methods for reading a charge previously stored in a column of charge trapping dielectric flash memory cells that is adjacent to an inactive column.
Conventional floating gate flash memory types of EEPROMs (electrically erasable programmable read only memory), utilize a memory cell characterized by a vertical stack of a tunnel oxide (SiO2), a polysilicon floating gate over the tunnel oxide, an interlayer dielectric over the floating gate (typically an oxide, nitride, oxide stack), and a control gate over the interlayer dielectric positioned over a crystalline silicon substrate. Within the substrate is a channel region, positioned below the vertical stack, and source and drain diffusions on opposing sides of the channel region.
The floating gate flash memory cell is programmed by inducing hot electron injection from the channel region to the floating gate to create a non volatile negative charge on the floating gate. Hot electron injection can be achieved by applying a drain to source bias along with a high control gate positive voltage. The gate voltage inverts the channel while the drain to source bias accelerates electrons towards the drain. The accelerated electrons gain 5.0 to 6.0 eV of kinetic energy which is more than sufficient to cross the 3.2 eV Sixe2x80x94SiO2 energy barrier between the channel region and the tunnel oxide. While the electrons are accelerated towards the drain, those electrons which collide with the crystalline lattice are re-directed towards the Sixe2x80x94SiO2 interface under the influence of the control gate electrical field and gain sufficient energy to cross the barrier.
Once programmed, the negative charge on the floating gate disburses across the semi conductive gate and has the effect of increasing the threshold voltage of the FET characterized by the source region, drain region, channel region, and control gate. During a xe2x80x9creadxe2x80x9d of the memory cell, the programmed, or non-programmed, state of the memory cell can be detected by detecting the magnitude of the current flowing between the source and drain at a predetermined control gate voltage.
More recently charge trapping dielectric flash memory cell structures have been developed. Each charge trapping dielectric flash memory cell is characterized by a vertical stack of an insulating tunnel layer, a charge trapping dielectric layer, an insulating top oxide layer, and a polysilicon control gate positioned on top of a crystalline silicon substrate.
The cells within the array may be arranged in a matrix such that bit lines are shared by cells within a column, and word lines are shared by cells within a row. More specifically, within the substrate is a channel region associated with each memory cell that is positioned below the vertical stack. One of a plurality of bit line diffusions separates each channel region from an adjacent channel region. The bit line diffusions form the source region and drain region of each cell. Each polysilicon control gate may be a portion of a polysilicon word line extending over the insulating top oxide layer of all cells such that all of the control gates are electrically coupled.
Similar to the floating gate device, the charge trapping dielectric flash memory cell is programmed by inducing hot electron injection from the channel region to the nitride layer to create a non volatile negative charge within charge traps existing in the nitride layer. Again, hot electron injection can be achieved by applying a drain-to-source bias along with a high positive voltage on the control gate. The high voltage on the control gate inverts the channel region while the drain-to-source bias accelerates electrons towards the drain region. The accelerated electrons gain 5.0 to 6.0 eV of kinetic energy which is more than sufficient to cross the 3.2 eV Sixe2x80x94SiO2 energy barrier between the channel region and the tunnel oxide. While the electrons are accelerated towards the drain region, those electrons which collide with the crystalline lattice are re-directed towards the Sixe2x80x94SiO2 interface under the influence of the control gate electrical field and have sufficient energy to cross the barrier. Because the nitride layer stores the injected electrons within traps and is otherwise a dielectric, the trapped electrons remain localized within a drain charge storage region that is close to the drain region.
Similarly, a source-to-drain bias may be applied along with a high positive voltage on the control gate to inject hot electrons into a source charge storage region that is close to the source region. For example, grounding the drain region in the presence of a high voltage on the gate and the source region may be used to inject electrons into the source bit charge storage region.
As such, the charge trapping dielectric flash memory cell device can be used to store two bits of data, one in each of the source charge storage region (referred to as the source bit) and the charge storage region (referred to as the drain bit).
Due to the fact that the charge stored in the storage region only increases the threshold voltage in the portion of the channel region beneath the storage region, each of the source bit and the drain bit can be read independently by detecting channel inversion in the region of the channel region beneath each of the source storage region and the drain storage region. To xe2x80x9creadxe2x80x9d the drain bit, the drain region is grounded while a voltage is applied to the source region and a slightly higher voltage is applied to the gate. As such, the portion of the channel region near the source/channel junction will not invert (because the gate voltage with respect to the source region voltage is insufficient to invert the channel) and current flow at the drain/channel junction can be used to detect the change in threshold voltage caused by the programmed state of the drain bit.
Similarly, to xe2x80x9creadxe2x80x9d the source bit, the source region is grounded while a voltage is applied to the drain region and a slightly higher voltage is applied to the gate. As such, the portion of the channel region near the drain/channel junction will not invert and current flow at the source/channel junction can be used to detect the change in threshold voltage caused by the programmed state of the source bit.
FIG. 1 shows a block diagram of a conventional array of charge trapping dielectric flash memory cells 16. Each pair of adjacent bit line diffusions 14a-14h form a source region and a drain region for each cell 16 within the column of cells 18 defined by such pair of adjacent bit lines 14. Each word line 12a-12e forms a semiconductor control gate over each cell 16 within the row 20a-20e of cells 16 that are defined by such word line 12.
The above described programming and reading of each charge trapping region of each cell 16 within the array 10 may be accomplish by applying appropriate programming voltage potentials and appropriate read voltage potentials to each bit line diffusion 14a-14h and each word line 12a-12e to individually program and read selected cells 16.
Erasing a programmed charge within a cell 16 is performed by coupling bulk erase voltage potentials to each bit line diffusion 14a-14h and each word line 12a-12e to bulk erase all cells 16 within the array 10 simultaneously. Bulk erase techniques using hot hole injection or the tunneling of the stored charge into the gate or the substrate are known in the art.
A problem associated with such conventional arrays is that certain columns may be inactive. For example, if testing of the array 10 indicates that cells within the columns 18b-18d do not operate properly, array control circuits may inactivate such columns 18b-18d such that no data is programmed to the cells therein.
A problem associated with inactive columns is over-erasure. While the cells within the inactive columns are not programmed and read, those cells due undergo erasure each time a bulk erase is performed on the array. Multiple sequential erase cycles can cause depletion in the charge storage region thereby lowering the threshold voltage of the cell even in its erased (un-programmed) state.
As such, when the word line associated with the over-erased cell is coupled to a read potential for reading a selected cell in a column adjacent to the inactive column, current leakage through the over-erased cell may cause mis-reading of the selected cell.
What is needed is an array system and method for operating an array of memory cells, which includes inactive columns, which does not suffer the disadvantages of known systems.
A first aspect of the present invention is to provide an array of non-volatile memory cells for storing a data pattern and reproducing the data pattern. The array comprises: a) a semiconductor substrate; b) a plurality of parallel and spaced apart bit line diffusions within the substrate defining a plurality of vertical channel regions spaced there between; c) a plurality of parallel spaced apart semiconductor word lines positioned over the substrate and separated from the substrate by an insulator film, a charge trapping layer, and a second insulator film, the word lines being perpendicular to the bit line diffusions and forming a memory cell at each intersection of a word line and a channel region; d) circuits for determining an inactive memory cell programming pattern; and e) an array control circuit coupled to each bit line diffusion and coupled to each word line.
Within the array, a block of inactive columns of memory cells may include a first inactive column and a second inactive column, both of which may be adjacent to, and share a bit line with, a first active column of memory cells and a second active column of memory cells. Between the first inactive column and the second inactive column there maybe one for more additional inactive columns.
The inactive memory cell programming pattern may identify a selected plurality of the memory cells within the first inactive column, the second inactive column, and the one or more additional inactive columns, in which a charge is to be stored for the purpose of periodically storing a charge in the source charge trapping region and the drain charge trapping region of the memory cells to prevent over erasure.
The inactive memory cell programming pattern preferably identifies all cells within the first inactive column and the second inactive column. Alternatively, the inactive memory cell programming pattern may be a pattern sequentially selected from a plurality of inactive programming patterns. The plurality of inactive programming patterns, in sequence, provide for storing a charge on each charge trapping region of each memory cell within the first inactive column and the second inactive column at least once prior to performing a predetermined number of sequential erase cycles. In either embodiment, the programming pattern may identify a selected plurality of memory cells within the at least one additional inactive column.
The array control circuit may comprise programming circuits, reading circuits and erase circuits. The programming circuits provide for coupling each bit line diffusion and each word line to programming potentials for storing a charge within a selected plurality of the memory cells within the first active column and within the second active column. The selected plurality of memory cells represents a portion of a data pattern. The programming circuit also provides for coupling each bit line diffusion and each word line to programming potentials for storing a charge within a selected plurality of the memory cells within the first inactive column, within the second inactive column, and/or within the at least one additional inactive column that represents an inactive memory cell programming pattern to prevent over-erasure of cells within such inactive columns.
The reading circuits provide for coupling each bit line diffusion and each word line to programming potentials for reproducing the portion of the input data pattern by reading each memory cell within the first active column and/or within the second active column.
The erase circuits provide for coupling all memory cells of all columns (e.g. the first active column, the second active column, the first inactive column, the second inactive column, and the at least one additional inactive column) to erase voltage potentials that provide for removing a stored charge.
A second aspect of the present invention is to provide a method of storing a data pattern and reproducing the data pattern within an array of non-volatile memory cells. Within the array, a block of inactive columns of memory cells may include a first inactive column and a second inactive column, both of which may be adjacent to, and share a bit line with, a first active column and a second active column. Between the first inactive column and the second inactive column there maybe one for more additional inactive columns.
The method comprises storing a charge within a selected plurality of the memory cells within the first active column and/or the second active column. The selected plurality of memory cells represents a portion of the data pattern. The portion of the data pattern is reproduced by reading each memory cell within the first active column and/or the second active column.
Erasing of the memory cells within the array again comprises coupling all memory cells to voltage potentials that provide for removing a stored charge from each memory cell.
To prevent over-erasure of memory cells within the first inactive column and/or the second inactive column, the method may further comprises determining an inactive memory cell programming pattern and programming all or selected memory cells within at least one of the first inactive column, the second inactive column, and the at least one additional inactive column in accordance therewith. The inactive memory cell programming pattern may identify a selected plurality of the memory cells in such columns in which a charge is to be stored for the purpose of periodically storing a charge to prevent over erasure. The inactive memory cell programming pattern may be a pattern that provides for storing a charge on all of the memory cells within such columns. Alternatively, the inactive memory cell programming pattern may be a pattern sequentially selected from a plurality of inactive programming patterns. The plurality of inactive programming patterns, in sequence, provide for storing a charge on each source charge trapping region and each drain charge trapping region of each memory cell within such columns at least once prior to performing a predetermined number of sequential erase cycles.
For a better understanding of the present invention, together with other and further aspects thereof, reference is made to the following description, taken in conjunction with the accompanying drawings. The scope of the invention is set forth in the appended clams.